INF-2026-0512RUBRIC: TECH LANDSCAPE · 14 PP
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Executive summary
The inference bottleneck: where capacity meets cost.
Compute supply for foundation-model inference is repricing along three vectors at once — power, memory bandwidth, and packaging. Each constraint resolves on a different timeline, and the order they unlock will determine which providers absorb the marginal workload through 2027.
3.4×
YoY inference demand growth, blended
22%
Price gap, leading vs prior gen
120d
Median packaging-capacity lead time
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Structured narrative
Inference demand is projected to grow [1] at roughly 3.4× year-over-year through 2027, while accelerator production remains throttled by HBM yield and CoWoS packaging capacity. The result is a sustained gap between booked and deliverable compute that flows through to enterprise pricing.
Hyperscalers have responded by [2] shifting to multi-vendor inference paths and pre-buying capacity from second-tier silicon providers. The shift narrows the price gap between bleeding-edge and one-generation-back hardware to less than 22%.
The constraint that resolves first — power, memory, or packaging — will decide which vendor lands the marginal hyperscaler workload.
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Inline citations
IEA — World Energy Outlook 2025PrimaryTSMC FY25 Q4 capacity disclosurePrimarySemiAnalysis HBM model, Mar 2026ModeledBain — Generative AI in the Enterprise 2026Peer-reviewed
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Source quality indicators
Each citation carries its tier — primary, peer-reviewed, or modeled — visible on the chip itself. Modeled claims aren’t suppressed; they’re labeled.
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Gap analysisProvider-specific allocation share past Q4 2026 could not be confirmed — disclosure is inconsistent across vendors and counter-party NDAs limit cross-checking.
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Follow-on questions
- →Which constraint will resolve first — power, memory, or packaging?
- →How does HBM3e ramp pacing change the 2027 forecast?
- →What does a 6-month packaging delay do to enterprise pricing?